Multi-Wafer Surface Ion Traps: Enhanced Trap Depth, Vertical Confinement, and Ion Lifetime Through Increased Wafer Separation

Abstract

Surface ion traps are a cornerstone technology for scalable quantum information processing, yet their shallow trap depths and limited ion lifetimes remain fundamental engineering bottlenecks. This study presents a systematic experimental and statistical comparison between standard single-wafer surface traps and a novel multi-wafer surface trap architecture in which two parallel wafers with integrated radio-frequency (RF) electrodes are separated by a controllable vertical gap. Seventeen trap configurations were characterized (N = 5 standard, N = 12 multi-wafer), with wafer separations ranging from 50 to 500 µm. Welch’s independent-samples t-tests revealed that the multi-wafer geometry produced a mean trap depth of 23.53 meV compared with 8.50 meV in standard traps (d = 2.71, p < .001), extended ion lifetimes from 120 s to 620.75 s (d = 2.72, p < .001), and reduced anomalous heating rates from 857 to 153 quanta/s (d = −14.75, p < .001). Pearson correlations showed an exceptionally strong positive relationship between wafer separation and trap depth (r = .999, p < .001), and between trap depth and ion lifetime (r = .997, p < .001). A linear regression model explained 99.4% of the variance in ion lifetime from trap depth alone (R² = .995). Qubit coherence time (T₂*) scaled with trap depth, reaching 18.2 ms in the deepest configuration. Results demonstrate that multi-wafer architectures overcome the characteristic depth saturation (∼5.5 meV) of standard designs and produce deeper, more stable, and longer-lived ion traps suitable for scalable quantum computing.

Keywords: surface ion trap, multi-wafer architecture, trap depth, ion lifetime, quantum computing, anomalous heating, vertical confinement